1. Technical Field
The present invention relates generally to a semiconductor apparatus, and more particularly, to a technology for controlling an output timing of output data according to data output delay information.
2. Related Art
A semiconductor apparatus operates in synchronization with a reference periodic pulse signal such as a clock, in order to increase an operation speed and ensure an efficient internal operation. Accordingly, most semiconductor apparatuses operate using a clock supplied form an outside or an internal clock generated therein.
Since a signal transmitted from a transmitter, e.g., a semiconductor memory apparatus may be affected by an environment, if data affected by the environment is transmitted from the transmitter without a clock which may be adjusted according to the environment, a receiver of the data may not sample the data correctly. Accordingly, the adjusted clock may be used to enhance timing characteristics, and a delay locked loop (DLL) or a phase locked loop (PLL) may be used to generate the adjusted clock.
If a read command is inputted to the semiconductor apparatus, a timing at which output data is to be outputted is controlled according to data output delay information. The data output delay information is information indicating after which clocks from a time at which the read command is inputted the output data is to be outputted.
In the case where a clock signal, which a semiconductor apparatus operates is using, varies, a timing margin required when controlling the output timing of output data may deteriorate.